The present invention relates to a clock network of an integrated circuit, and more particularly, to a clock buffer circuit for a clock network.
An integrated circuit (IC) includes a plurality of internal circuits that receive a clock signal and operate in synchronism with the clock signal. Each internal circuit receives the clock signal via one or more clock buffers. However, there is a limit to the number of internal circuits that can be operated by a clock signal originating from a single clock buffer. Additionally, to meet the timing of the circuit, it is essential to keep the clock latency and skew (between different internal circuits receiving the clock inputs), within prescribed limits. Thus, to provide the clock signal to a plurality of internal circuits, the IC includes a plurality of clock networks, each including a plurality of clock buffers.
The recent tendency for the use of more internal circuits has increased the number of clock buffers in a clock network. However, as is well known, clock buffers slow down the clock signal and contribute to the problem of clock skew. Thus, there is a demand for faster clock buffers. To increase the speed of a clock buffer circuit, faster transistors can be used to form the circuit, such as low voltage threshold (LVT) transistors. However, LVT transistors increase power consumption and their use is thus in conflict with today's demands for low power circuits.
Thus, it would be desirable to have a low power but fast clock buffer circuit.